1. Field of the Invention
The present invention relates to a memory and a method of fabricating the same, and more particularly, it relates to a memory such as a mask ROM and a method of fabricating the same.
2. Description of the Background Art
In general, a mask ROM is known as an exemplary memory, as disclosed in Japanese Patent Laying-Open No. 5-275656 (1993), for example.
FIG. 32 is a plane layout diagram showing the structure of a conventional contact-type mask ROM. FIG. 33 is a sectional view of the conventional contact-type mask ROM taken along the line 500-500 in FIG. 32. Referring to FIGS. 32 and 33, a plurality of impurity regions 102 containing an impurity diffused therein are formed on the upper surface of a substrate 101 at prescribed intervals in the conventional contact-type mask ROM. A word line 104 functioning as a gate electrode is formed on an upper surface portion of the substrate 101 corresponding to a clearance between each adjacent pair of impurity regions 102 through a gate insulating film 103. This word line 104, the gate insulating film 103 and the corresponding pair of impurity regions 102 form each transistor 105. A first interlayer dielectric film 106 is formed to cover the upper surface of the substrate 101 and the word lines 104. The first interlayer dielectric film 106 has contact holes 107 formed in correspondence to the respective impurity regions 102, and first plugs 108 are embedded in the contact holes 107 to be connected to the impurity regions 102 respectively.
Source lines (GND lines) 109 and connection layers 110 are provided on the first interlayer dielectric film 106, to be connected to the first plugs 108. Each transistor 105 is provided every memory cell 111. A second interlayer dielectric film 112 is formed on the first interlayer dielectric film 106 to cover the source lines (GND lines) 109 and the connection layers 110. Contact holes 113 are formed in regions of the second interlayer dielectric film 112 located on prescribed ones of the connection layers 110, while second plugs 114 are embedded in the contact holes 113. Bit lines 115 are formed on the second interlayer dielectric film 112, to be connected to the second plugs 114. Thus, the bit lines 115 are connected with the impurity regions 102 of the transistors 105.
In the conventional contact-type mask ROM, those of the transistors 105 provided with the second plugs 114 are connected (contacted) to the corresponding bit lines 115. Each memory cell 111 stores data “0” or “1” in response to whether or not the transistor 105 included therein is connected to the corresponding bit line 115.
In the conventional mask ROM shown in FIG. 32, however, the memory cell size is disadvantageously increased due to the transistors 105 provided in correspondence to the respective memory cells 111.